In recent times, there is a rapidly increasing demand for semiconductor devices that have higher density, higher speed, and higher capacity transmission. Particularly from the viewpoint of downscaling of semiconductor devices, rapid progress in downscaling is predicted (FIG. 14) in the 2003 Edition of the ITRS (International Technology Roadmap for Semiconductors) roadmap, i.e., that the pitch of peripherally disposed electrodes will be reduced from 35 μm in 2004 to 20 μm in 2009, and that the pitch of area disposed electrodes with be reduced from 150 μm in 2004 to 100 μm in 2009. In such conditions, semiconductor device testing techniques having a very small pitch has been one key technology. In semiconductor device manufacturing in particular, the problem that involves the manner in which elements are electrically tested in the wafer state, i.e., the manner in which wafer testing is carried out, is very critical in terms of contributing to improvements in quality via rapid feedback of problems in the wafer manufacturing process, reliably removing defective products and increasing the production yield rate during mass production of semiconductor devices, and ensuring lower costs by achieving higher productivity.
Conventional wafer testing is largely classified into contact schemes and non-contact schemes in terms of sending and receiving signals. Currently, contact schemes that are mainly used are those in which some type of contact terminal is brought into contact with the electrodes of a semiconductor device by using a probe card as an interface for sending and receiving signals between a wafer and a tester. The most commonly used contact terminal is a probe card referred to as a cantilever, and is a scheme for bringing metal needles into contact with the electrodes of the semiconductor device. Other contact schemes include those that use a membrane sheet having metal protrusions (bumps), those that use a membrane sheet having TCP (Tape Carrier Package) leads, and those that use a pin-shaped silicon probe in which a plated silicon whisker is used.
Known non-contact schemes include schemes in which a coil for communication is disposed in a semiconductor apparatus and signal input/output is wirelessly carried out with the exterior; schemes in which a chip having a structure that mirrors that of a semiconductor device is used to bring the signal wiring of a semiconductor apparatus and the wiring of the mirror chip into close proximity with each other, whereby signals are brought out by non-contact capacitive coupling; and the like. Patent document 1 discloses a cantilever scheme that uses metal needles, patent document 2 discloses a membrane sheet having metal protrusions, patent document 3 discloses a membrane sheet having TCP leads, and patent document 4 discloses the use of a silicon whisker. Patent document 5 discloses a scheme for using a coil for communication, and patent document 6 discloses a scheme for bringing out signals by way of non-contact capacitive coupling. First, the prior arts of contact schemes are described below.
(1) Cantilever Scheme Using Metal Needles (Patent Document 1) (First Prior Art)
This scheme involves machining tungsten, rhenium tungsten, and other metal needles and using the needles as contact terminals. The distal ends of metal needles 150 having a base diameter of 190 μm are machined to ultra fine wires in the manner shown in FIG. 17 in order to provide the metal needles with a narrow pitch. The plurality of machined metal needles 150 is provided with insulation therebetween by using a shielding plate 151, and is stacked in four tiers. Such a structure allows the pitch of the distal ends of the contact terminals to be narrowed to a pitch of 50 μm.
(2) Scheme for Using a Membrane Sheet Having Metal Protrusions (Bumps) (Patent Document 2) (Second Prior Art)
The “thin film probe cushioning system having bump contacts” of patent document 7 and the “probe card” of patent document 8 are known in addition to patent document 2. These prior arts are probe structures that use a contact sheet having metal protrusions (bumps) in positions that face the external electrodes of a semiconductor device. FIG. 18 shows a typical example of a portion of a probe card structure, and a scheme for manufacturing the same described in patent document 2.
In FIG. 18, a desired test circuit pattern (not shown) and an electrode lead 161 are formed on one surface of a flexible insulation film 160 that constitutes the probe card. A metal protrusion (bump) 162 is formed at the distal end of the electrode lead 161 in a position that faces external terminal electrodes 166 of a semiconductor device 165. The probe card makes contact with the external terminal electrodes 166 of the semiconductor device 165 by way of the metal protrusion 162.
(3) Scheme for Using a Membrane Sheet Having TCP Projections (Patent Document 3) (Third Prior Art)
Prior arts similar to patent document 3 are disclosed in patent documents 9, 10, and 11. These prior arts have a probe structure in which a flexible substrate having metal leads is used in a position that faces the external electrodes of a semiconductor device.
FIG. 19 shows a structural diagram of the probe card disclosed in patent document 3 as a typical example. FIG. 19(a) is a cross-sectional view of the essential parts on one side of the probe card, and FIG. 19(b) is a perspective cutaway view showing a portion of the probe card. A desired testing circuit pattern (not shown) and a probe pin 172 are formed on one side of a flexible film 171. The probe pin 172 makes contact with the external electrode of a semiconductor device 175.
The probe pin 172 is disposed at a distal end portion of the testing circuit pattern, and the wiring pattern of the probe pin is supported by the film 171. The wiring pattern, probe pin 172, and film 171 constitute as a whole a flexible substrate (FPC) 170. The flexible substrate 170 is thin and therefore cannot achieve a desired contact force by itself. For this reason, the probe card is provided with dampers 173a and 173b and a support body 174 that support the flexible substrate 170 on both surfaces thereof. The probe pin 172 is thereby configured to reliably make contact with an external electrode of the semiconductor device 175.
The support body 174 is made of stainless steel or brass. The support body 174 has a sloped surface in the front (right side in FIG. 19(a)) that receives the portion of the flexible substrate 170 proximate to the probe pin 172, and has a horizontal mounting surface in the rear (left side in FIG. 19(a)) on the card substrate (not shown). The sloped surface is a trapezoidal shape in which the front end portion is a short side as viewed from above in the manner shown in FIG. 19(b).
The probe card is provided with a hard reinforcement plate 176 made of stainless steel, and a printed substrate 177 having a wiring pattern on the upper surface. The printed substrate 177 is reinforced by the reinforcement plate 176 to constitute a hard card substrate. The damper 173a is also a trapezoidal plate in which the front end portion is the short side (see FIG. 19(b)). The damper 173a is mounted on the support body 174 by using a bolt 179a in a superimposed state on the flexible substrate 170 and the insulation sheet 178, which is superimposed on the sloped surface of the support body 174. The damper 173b is mounted on the support body 174 by using a bolt 179b in a superimposed state on the horizontal surface of the support body 174, with the flexible substrate 170 disposed therebetween.
The damper 173a thereby fastens the portion of the flexible substrate 170 disposed toward the probe pin 172 to the sloped surface of the support body 174 from above, and supports the probe pin 172 from above at the front edge portion thereof.
(4) Probe for Wafer Testing Using a Silicon Whisker as a Contact Terminal (Patent Document 4) (Fourth Prior Art)
Art similar to the prior art described in patent document 12 is disclosed in patent documents 13 and 14. FIG. 20 shows a structural diagram of a probe pin and contactor having the probe pin disclosed in patent document 12 as a typical example.
The probe pin shown in FIG. 20 has a structure in which a needle-shaped single crystal 181 is grown on a silicon substrate 180, an Ni under film 182 and an Au film 183 are furthermore formed on the surface of the needle-shaped single crystal 181, and a Pd film 184 is formed at the distal end of the Au film 183. In other words, an Au seed is disposed on the silicon substrate 180, and a needle-shaped single crystal 181 composed of silicon is formed by VLS growth. The probe pin in the diagram is used to measure a semiconductor provided with an electroconductive film on the surface of the needle-shaped single crystal 181, and has a structure in which only the distal end portion is covered by a contact point material.
Next, prior arts of non-contact schemes will be described.
(5) Non-contact Testing Scheme Using a Coil for Communication (Patent Document 5) (Fifth Prior Art)
The structure based on this scheme, and the corresponding testing method will be described with reference to FIGS. 21(a) to 21(c). FIG. 21(a) is a plan view of the wafer 190, and a plurality of semiconductor chips 196 is formed on the wafer 190. FIG. 21(b) is an enlarged view of the round frame portion in which the semiconductor chip 196 is disposed on the wafer 190 in FIG. 21(a). Coils 192A and 192B for communication, which are used exclusively for semiconductor testing, are formed on the semiconductor chips 191A and 191B, respectively, as shown in FIG. 21(b); and the coils 192A and 192B and connection terminals 193A and 193B are connected by wirings 194A and 194B, respectively. The coils 192A and 192B for communication are both rectangular spiral-shaped coils and are formed on the circuit surface side of the semiconductor chips 191A and 191B via an insulating surface-protecting film. Two wires are formed on the coil for communication, one of the wires is connected to the connection terminal inside the semiconductor chip, and the other wire is connected to a connection terminal by way of a scribe line.
Testing is carried out in the manner shown in FIG. 21(c) using a semiconductor chip having this structure. In other words, a testing signal is wirelessly outputted from a head 195 of the semiconductor device to the communication coil 192A of the semiconductor chip 191A. The function of the semiconductor chip 191A is tested by receiving the output signal from the corresponding semiconductor chip 191A. The head 195 or semiconductor chip is moved, whereby the semiconductor chips are tested in a sequential manner.
(6) Non-contact Testing Scheme Using Capacitive Coupling (Patent Document 6) (Sixth Prior Art)
FIG. 22 shows a structural diagram of the invention disclosed in patent document 6. In a voltage probe chip 210, sensor units 211 are disposed in mutually corresponding positions to the signal wires 201 that are to be monitored in an LSI chip 200. Voltage variations of the semiconductor chip 200 are detected by the voltage probe chip 210 as induced voltage brought about by electrostatic induction.
More specifically, the voltage probe chip 210 is composed of an amplifier or another signal processing circuit 213 formed on a silicon substrate 212, sensor units 211 arrayed in mutually corresponding positions to the signal wires 201 in the LSI chip 200, and silicate glass (dielectric material layer) 214 having a thickness of 0.5 μm on the surface of the sensor units 211. The surface of the dielectric material layer 214 is smoothly polished.
The LSI chip 200 has a wiring layer 203 formed on the surface of a silicon substrate 202, and has signal wires 201 disposed at fixed intervals on the surface of an interlayer insulation film 204 that is formed on the wiring layer 203. The wiring layer 203 is connected to signal wire electrodes of the signal wires 201 via through-holes provided to the interlayer insulation film 204. The surface of the interlayer insulation film 204 in which the signal wire electrode is exposed has been made flat by CMP (chemical-mechanical polishing) or the like.
The electrodes of the signal wires 201 of the LSI chip 200 and the sensor units 211 of the voltage probe chip 210 are positionally aligned, pressure is applied by vacuum suctioning, and chips are fixed in place by direct bonding. In this state, the LSI chip 200 is driven by applying voltage to external lead terminals (not shown). The induction voltage at this time is detected by the sensor units 211 of the voltage probe chip 210 and monitored via the signal processing circuit 213.
Patent Document 1: U.S. Pat. No. 5,969,533
Patent Document 2: Japanese Laid-open Patent Application No. 5-226430
Patent Document 3: Japanese Laid-open Patent Application No. 6-334006
Patent Document 4: Japanese Laid-open Patent Application No. 11-190748
Patent Document 5: Japanese Laid-open Patent Application No. 2003-273180
Patent Document 6: Japanese Laid-open Patent Application No. 2003-344448
Patent Document 7: Japanese Laid-open Patent Application No. 5-243344
Patent Document 8: WO 98/58266
Patent Document 9: Japanese Laid-open Patent Application No. 6-334005
Patent Document 10: Japanese Laid-open Patent Application No. 6-331655
Patent Document 11: Japanese Laid-open Patent Application No. 6-324081
Patent Document 12: Japanese Laid-open Patent Application No. 10-038918
Patent Document 13: Japanese Laid-open Patent Application No. 2002-257859
Patent Document 14: Japanese Laid-open Patent Application No. 5-198636